1. Field of the Invention
The present invention relates to semiconductor devices and manufacturing methods thereof. Particularly, the present invention relates to a semiconductor device having an impurity concentration profile applied to a contact region between a semiconductor substrate and a conductive layer, and a manufacturing method thereof.
2. Description of the Background Art
In accordance with the recent significant increase in the integration density of a semiconductor integrated circuit device, microminiaturization of elements has evolved rapidly. Particularly in a dynamic random access memory (DRAM) which is one semiconductor memory device, the integration density of the memory is increased corresponding to increase in the storage capacity such as from 64 megabits to 256 megabits, and further to 1 gigabit. Field effect transistors and capacitors functioning as active elements constituting a highly integrated memory must have miniaturized structures. The diameter of the contact with the impurity region of a semiconductor substrate is also reduced corresponding to miniaturization of the active elements.
The leakage current flowing from the contact to the semiconductor substrate will result in a great amount in one semiconductor device as the number of contacts formed in one device becomes greater in association with the integration of the active elements. In forming a highly integrated semiconductor device, the ratio of the leakage current to the entire power consumption will take a great value. Furthermore, there is a problem that the operating voltage of an active element, for example a field effect transistor, will be limited due to a lower junction breakdown voltage at the contact caused by increase in the impurity concentration of the semiconductor substrate by scaling of active elements.
FIG. 21 is a partial sectional view of a conventional contact structure. As shown in FIG. 21, an n type impurity region 106 including n type impurities is formed having a predetermined depth from the surface of a p type silicon substrate 101. A contact hole 116 is formed in an interlayer insulation film 115 so as to expose the surface of n type impurity region 106. A conductive layer 110, for example an electrode layer, a storage node of a capacitor, is formed so as to come into contact with the surface of n type impurity region 106 through contact hole 116.
In the above contact structure, ions for preventing leakage current are implanted, if necessary, after contact hole 116 is formed. Then, a conductive material such as polycrystalline silicon having n type impurities doped is introduced into contact hole 116 to form conductive layer 110.
FIG. 22 shows the impurity concentration profile at the position of XXII of FIG. 21. As shown in FIG. 22, silicon substrate 101 has an impurity concentration profile p(B) in which boron (B) is introduced as the p type impurity. N type impurity region 106 has an impurity concentration profile n(P) in which phosphorus (P) is introduced as the n type impurity. The junction point J where the curves of these two impurity concentration profiles cross each other has a concentration of approximately 1.times.10.sup.17 cm.sup.-3.
At the region of the silicon substrate including the above-described impurity concentration profile, a p type impurity region for adjusting the threshold voltage of a field effect transistor and a p type impurity region for preventing inversion, formed at a region beneath an element isolation insulation film, are formed so as to extend over an element formation region. In this case, the p type impurity concentration increases at shallow regions in the p type impurity concentration profile p(B). The position of junction point J is shifted towards a higher impurity concentration. When a voltage is applied to conductive layer 110, a depletion layer cannot easily spread since the impurity concentration is great at the pn junction to induce the possibility of electric field concentration. Particularly, the problem of reduction in the junction breakdown voltage due to increase in the impurity concentration at the pn junction is noted. There was also the problem of a greater leakage current in the contact structure due to increase in the impurity concentration at the pn junction.
U.S. patent application Ser. No. 08/709,592 discloses a contact structure for preventing reduction in the junction breakdown voltage and increase in leakage current.
FIG. 23 is a partial sectional view of a contact structure disclosed in the aforementioned application. Referring to FIG. 23, a p type well formation dope region 103, a p type channel cut region (inversion prevention region) 104, and a p type channel dope region 105 (for adjusting threshold voltage) with respective predetermined depth are formed at a p type silicon substrate 101. An n type impurity region 106 is formed at p type silicon substrate 101. A contact hole 116 exposing the surface of n type impurity region 106 is formed in an interlayer insulation layer 115. A conductive layer 110 is formed so as to come into contact with the surface of n type impurity region 106 via contact hole 116.
FIG. 24 shows an impurity concentration profile at a position XXIV of FIG. 23. As shown in FIG. 24, a p type impurity concentration profile p(B) includes impurity concentration peaks respectively corresponding to p type well formation dope region 103, p type channel cut region 104, and p type channel dope region 105. An n type impurity concentration profile n(P)exhibits values higher than the respective impurity concentrations of p type channel cut region 104 and p type channel dope region 105 at predetermined depth thereof. N type impurity concentration profile n(P) has a junction point J in the proximity of a minimum value X of p type impurity concentration profile p(B).
As described above, the position of the pn junction is located at a low impurity concentration level in both the n type impurity concentration profile n(P) and p type impurity concentration profile p(B). Therefore, in comparison to the case where junction point J is located at a high impurity concentration level, the depletion layer is easily depleted to exhibit a greater expansion even when the voltage applied to conductive layer 110 is identical. The junction does not break down until the voltage applied to the contact becomes higher. Therefore, the junction breakdown voltage is improved. As a result, the electric field generated at the pn junction is mitigated to reduce the leakage current generated at the contact region.
FIG. 25 is a partial sectional view of a memory portion of a DRAM in which an impurity concentration profile as shown in FIG. 24 is applied. Referring to FIG. 25, a gate electrode 109 is formed on a p type silicon substrate 101 with a gate insulation film 108 thereunder. A pair of n type source/drain regions 106 and 107 are formed at a surface region of silicon substrate 101 at both sides of gate electrode 109. A storage node 110 is formed so as to come into contact with the surface of one source/drain region 106. A dielectric film 111 is formed so as to cover the surface of storage node 110. A cell plate 112 is formed so as to cover the surface of dielectric film 111. A capacitor is formed of storage node 110, dielectric film 111, and cell plate 112. A bit line 113 is formed so as to come into contact with the other source/drain region 107. Storage node 110 comes into contact with n type source/drain region 106 through a contact hole 116 formed in an interlayer insulation film 115. N type source/drain region 106 is formed of a region into which arsenic (As) is introduced, and a region including phosphorus (P) provided to improve the breakdown voltage of the pn junction and to suppress leakage current, as described above.
FIG. 26 shows the impurity concentration profile at a position XXVI of FIG. 25. As shown in FIG. 26, a p type impurity concentration profile p(B) has respective impurity concentration peaks corresponding to p type well formation dope region 103, p type channel cut region 104, and p type channel dope region 105. An n type impurity concentration profile n(P) exhibits an impurity concentration at the position between p type channel cut region 104 and p type channel dope region 105 higher than respective values thereat. N type impurity concentration profile n(P) has a pn junction point J in the proximity of a minimum value X of p type impurity concentration profile p(B). Thus, the junction breakdown voltage is improved, and the leakage current due to electric field mitigation is reduced. In FIG. 26, an n type impurity concentration profile n(As) in which arsenic (As) is introduced to form the original source/drain region is also shown.
In the memory portion of a DRAM having an impurity concentration profile as shown in FIG. 26, miniaturization of the field effect transistor is advanced according to increase of the storage capacity. In a DRAM having a memory capacity of approximately 1 gigabit, the gate has a length L of approximately 0.15 .mu.m in the field effect transistor shown in FIG. 25. The distance D between the sidewall of contact hole 116 and the sidewall of gate electrode 109 becomes as small as 0.075 .mu.m. In accordance with miniaturization of a field effect transistor, p type channel dope region 105 is formed so as to have a shallow and abrupt concentration gradient in FIG. 26. Therefore, as shown by the arrow in FIG. 26, n type source/drain region 106 is formed to have an n type impurity concentration profile n(P) exhibiting a higher impurity concentration at the shallow region. As a result, the region of n type source/drain region 106 where phosphorus (P) is introduced to mitigate the electric field and to improve the junction breakdown voltage is formed so as to have a higher concentration at the shallow region and to spread laterally as indicated by the chain line with two dots in FIG. 25.
The formation of the above n type source/drain region 106 induces problems set forth in the following.
The lateral spread of n type source/drain region 106 indicated by the chain line with two dots in FIG. 25 causes the field effect transistor to be easily turned on at a threshold voltage lower than that of the designed value. In other words, the characteristic of the field effect transistor is altered. For example, the threshold voltage is reduced. As a result, electrons of storage node 110 will easily leak out.
Also, alteration in distance D in FIG. 25 causes variation in the level of the effect of the spread of n type source/drain region 106 indicated by the chain line with two dots on the characteristics of the field effect transistor. This means that the characteristics of the field effect transistor is altered by variation in the position of contact hole 116. Therefore, the characteristics of the field effect transistor is altered by variation in the step of forming contact hole 116 and the manufacturing process conditions. In other words, the characteristics of the field effect transistor is susceptible to the variation in the formation position of storage node 116.